1. Field of the Invention
The present invention relates to phase-locked oscillation circuits and, more particularly, to a phase-locked oscillation circuit for use in a high-speed communication system requiring low jitter characteristics.
2. Description of the Related Art
In a conventional phase-locked oscillation circuit, as described in Japanese Patent Laid-Open Application No. Hei 7-283726, it is so designed to have its loop gain small so as to eliminate phase noise in an output clock signal generated by the phase-locked oscillation circuit.
FIG. 7 is a schematic block diagram showing a configuration of a conventional phase-locked oscillation circuit. In the drawing, a phase-locked oscillation circuit (PLO) 20 comprises, a phase comparator 3, a Low Pass Filter (LPF) 4, an Amplifier (AMP) 5, a Voltage Control Oscillator (VCO or VCXO) 6, a frequency divider 7, resistors 21, 22 and 23, and a switch 8. A reference signal 10 in synchronism with a local oscillator or a network synchronization timing signal is frequency-multiplied by the PLO 20 to form a clock signal 30 of a communication line speed. The PLO 20 is designed for clock generation for the purpose of generating a communication line timing signal, and it requires, in addition to input and output signals, a power supply ground signal and an input signal for control of VCO or VCXO 6.
In the aforementioned conventional phase-locked oscillation circuit used for clock frequency multiplication, since the frequency of a phase comparison signal is lower than that of the output clock signal of the phase-locked oscillation circuit, the phase fluctuation is averaged by frequency-dividing the output clock signal by a frequency divider circuit, but no countermeasures are taken into account to suppress the phase fluctuation caused by noise passed from a power supply.